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1/13 july 2001 n high speed: f max = 125mhz (typ.) at v cc = 5v n low power dissipation: i cc = 8 m a(max.) at t a =25c n high noise immunity: v nih = v nil = 28 % v cc (min.) n 50 w transmission line driving capability n symmetrical output impedance: |i oh | = i ol = 24ma (min) n balanced propagation delays: t plh @ t phl n operating voltage range: v cc (opr) = 2v to 6v n pin and function compatible with 74 series 161 n improved latch-up immunity description the 74ac161 is an advanced high-speed cmos syncronous presettable counter fabricated with sub-micron silicon gate and double-layer metal wiring c 2 mos tecnology. it is a 4 bit binary counter with asynchronous clear. the circuit have four fundamental modes of operation, in order of preference: synchronous reset, parallel load, count-up and hold. four control inputs, (clear ), (load ), (pe) and (te), determine the mode of operation as shown in the truth table. a low signal on clear overrides counting and parallel loading and sets all outputs on low state. a low signal on load overrides counting and allows information on parallel data inputs to be loaded into the flip-flop on the next rising edge of clock. with load and clear high, pe and te permit counting when both are high. conversely, a low signal on either pe and te inhibits counting. the carry output is high when te is high and counter is in state 15. all inputs and outputs are equipped with protection circuits against static discharge, giving them 2kv esd immunity and transient excess voltage. 74ac161 synchronous presettable 4-bit counter pin connection and iec logic symbols order codes package tube t & r dip 74ac161b sop 74ac161m 74AC161MTR tssop 74ac161ttr tssop dip sop
74ac161 2/13 input and output equivalent circuit pin description truth table x : dont care; a, b, c, d; logic level of data input; carry out : te x qa x qb x qc x qd logic diagram pin no symbol name and function 1 clear master reset 2 clock clock input (low to high edge trigger) 3, 4, 5, 6 a, b, c, d data inputs 7 pe count enable input 10 te count enable carry input 9load parallel enable input 14, 13, 12, 11 qa toqd flip-flop outputs 15 carry out terminal count output 8 gnd ground (0v) 16 v cc positive supply voltage inputs outputs function clear load pe te ck lxxxxl l l lpreset to "0" h l x x a b c d preset data h h x l no change no count h h l x no change no count hhhh count up count h x x x no change no count
74ac161 3/13 timing chart
74ac161 4/13 absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditi ons is not implied. recommended operating conditions 1) v in from 30% to 70% of v cc symbol parameter value unit v cc supply voltage -0.5 to +7 v v i dc input voltage -0.5 to v cc + 0.5 v v o dc output voltage -0.5 to v cc + 0.5 v i ik dc input diode current 20 ma i ok dc output diode current 20 ma i o dc output current 50 ma i cc or i gnd dc v cc or ground current 300 ma t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c symbol parameter value unit v cc supply voltage 2 to 6 v v i input voltage 0 to v cc v v o output voltage 0 to v cc v t op operating temperature -55 to 125 c dt/dv input rise and fall time v cc = 3.0, 4.5 or 5.5v (note 1) 8 ns/v
74ac161 5/13 dc specifications 1) maximum test duration 2ms, one output loaded at time 2) incident wave switching is guaranteed on transmission lines with impedances as low as 50 w symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. v ih high level input voltage 3.0 v o = 0.1 v or v cc -0.1v 2.1 1.5 2.1 2.1 v 4.5 3.15 2.25 3.15 3.15 5.5 3.85 2.75 3.85 3.85 v il low level input voltage 3.0 v o = 0.1 v or v cc -0.1v 1.5 0.9 0.9 0.9 v 4.5 2.25 1.35 1.35 1.35 5.5 2.75 1.65 1.65 1.65 v oh high level output voltage 3.0 i o =-50 m a 2.9 2.99 2.9 2.9 v 4.5 i o =-50 m a 4.4 4.49 4.4 4.4 5.5 i o =-50 m a 5.4 5.49 5.4 5.4 3.0 i o =-12 ma 2.56 2.46 2.4 4.5 i o =-24 ma 3.86 3.76 3.7 5.5 i o =-24 ma 4.86 4.76 4.7 v ol low level output voltage 3.0 i o =50 m a 0.002 0.1 0.1 0.1 v 4.5 i o =50 m a 0.001 0.1 0.1 0.1 5.5 i o =50 m a 0.001 0.1 0.1 0.1 3.0 i o =12 ma 0.36 0.44 0.5 4.5 i o =24 ma 0.36 0.44 0.5 5.5 i o =24 ma 0.36 0.44 0.5 i i input leakage current 5.5 v i = v cc or gnd 0.1 1 1 m a i cc quiescent supply current 5.5 v i = v cc or gnd 880160 m a i old dynamic output current (note 1, 2) 5.5 v old = 1.65 v max 75 50 ma i ohd v ohd = 3.85 v min -75 -50 ma
74ac161 6/13 ac electrical characteristics (c l = 50 pf, r l = 500 w , input t r = t f = 3ns) (*) voltage range is 3.3v 0.3v (**) voltage range is 5.0v 0.5v symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. t plh t phl propagation delay time clock to q 3.3 (*) 7.0 12.0 13.0 13.0 ns 5.0 (**) 5.0 9.0 10.0 10.0 t plh t phl propagation delay time clock to carry out 3.3 (*) 8.5 14.0 15.0 15.0 ns 5.0 (**) 6.0 10.0 11.0 11.0 t plh t phl propagation delay time te to carry out 3.3 (*) 5.5 9.5 11.0 11.0 ns 5.0 (**) 3.5 6.5 7.5 7.5 t phl propagation delay time clear to q 3.3 (*) 6.5 12.0 13.0 13.0 ns 5.0 (**) 5.5 9.0 10.0 10.0 t phl propagation delay time clear to carry out 3.3 (*) 7.0 12.0 13.0 13.0 ns 5.0 (**) 5.5 9.5 10.0 10.0 t wl clear pulse width low 3.3 (*) 3.0 5.5 7.5 7.5 ns 5.0 (**) 2.5 4.5 6.0 6.0 t w clock pulse width high or low 3.3 (*) 2.0 3.5 4.0 4.0 ns 5.0 (**) 2.0 3.0 3.5 3.5 t s setup time high or low (input to clock) 3.3 (*) 4.0 13.5 16.0 16.0 ns 5.0 (**) 1.5 8.5 10.5 10.5 t h hold time high or low (input to clock) 3.3 (*) -1.0 -1.0 0.5 0.5 ns 5.0 (**) -0.5 0.5 1.0 1.0 t s setup time high or low (clear to clock) 3.3 (*) 3.0 11.5 14.0 14.0 ns 5.0 (**) 2.0 7.5 8.5 8.5 t h hold time high or low (clear to clock) 3.3 (*) -2.5 0 0 0 ns 5.0 (**) -2.0 0.5 1.0 1.0 t s setup time high or low (pe or te to clock) 3.3 (*) 3.0 6.0 7.0 7.0 ns 5.0 (**) 2.0 4.5 5.0 5.0 t h hold time high or low (pe or te to clock) 3.3 (*) -1.0 0 0 0 ns 5.0 (**) -0.5 0 0.5 0.5 t rem recovery time (clear to clock) 3.3 (*) -1.0 0 0.5 0.5 ns 5.0 (**) -0.5 0.5 1.0 1.0 f max maximum clock frequency 3.3 (*) 70 90 60 60 mhz 5.0 (**) 110 125 95 95
74ac161 7/13 capacitive characteristics 1) c pd is defined as the value of the ics internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) = c pd x v cc x f in + i cc /n (per circuit) test circuit c l = 50pf or equivalent (includes jig and probe capacitance) r l = r 1 = 500 w or equivalent r t = z out of pulse generator (typically 50 w ) waveform 1: propagation delays, count mode (f=1mhz; 50% duty cycle) symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. c in input capacitance 5.0 4.5 pf c pd power dissipation capacitance (note1) 5.0 f in = 10mhz 18 pf
74ac161 8/13 waveform 2: propagation delays clear mode (f=1mhz; 50% duty cycle) waveform 3: propagation delays preset mode (f=1mhz; 50% duty cycle)
74ac161 9/13 waveform 4: propagation delays countable mode (f=1mhz; 50% duty cycle) waveform 5: propagation delays cascade mode (f=1mhz; 50% duty cycle)
74ac161 10/13 dim. mm. inch min. typ max. min. typ. max. a1 0.51 0.020 b 0.77 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 d 20 0.787 e 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 f 7.1 0.280 i 5.1 0.201 l 3.3 0.130 z 1.27 0.050 plastic dip-16 (0.25) mechanical data p001c
74ac161 11/13 dim. mm. inch min. typ max. min. typ. max. a 1.75 0.068 a1 0.1 0.2 0.003 0.007 a2 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 c 0.5 0.019 c1 45 (typ.) d 9.8 10 0.385 0.393 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 f 3.8 4.0 0.149 0.157 g 4.6 5.3 0.181 0.208 l 0.5 1.27 0.019 0.050 m 0.62 0.024 s8 (max.) so-16 mechanical data po13h
74ac161 12/13 dim. mm. inch min. typ max. min. typ. max. a 1.2 0.047 a1 0.05 0.15 0.002 0.004 0.006 a2 0.8 1 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 d 4.9 5 5.1 0.193 0.197 0.201 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 bsc 0.0256 bsc k0 80 8 l 0.45 0.60 0.75 0.018 0.024 0.030 tssop16 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 0080338d
74ac161 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco singapore - spain - sweden - switzerland - united kingdom ? http://www.st.com 13/13

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